#ifndef __CAN_FUNC_C__
#define __CAN_FUNC_C__

#include "can_var.c"


void delay(char time)
{
	char i,j;
	for(i=0;i<=time;i++)
	  for(j=0;j<=time;j++);

}
//Initial can, set bustiming 0/1 & choose basic mode & set acceptance code

void test_info(char * str)
{
	char i;

	i = 0;
	while(*(str+i)!='\0')
	{
	 	*info++ = *(str+i);
		i++;
	}
	*info++ = '\n';
}

void InitCan_Basic(char bustiming0, char bustiming1, char accep_code,char accep_mask)
{
	 EO = 0;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	// CAN_BUSTIMING0 = 0x43;		//sjw = 01b; BRP = 000011b
	// CAN_BUSTIMING1 = 0x2F;		//sam = 0(sigle sample)
	 CAN_BUSTIMING0 = bustiming0;
	 CAN_BUSTIMING1 = bustiming1;
	 CAN_CLOCK_DIVIDER = 0x00;	//choose basic mode;
	 CAN_BASIC_ACCEP_CODE = accep_code;
	 CAN_BASIC_ACCEP_MASK = accep_mask;
}

//Initial can, set bustiming 0/1 & choose basic mode & set acceptance code
void InitCan2_Basic(char bustiming0, char bustiming1, char accep_code,char accep_mask)
{
	 EO = 0x80;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	// CAN_BUSTIMING0 = 0x43;		//sjw = 01b; BRP = 000011b
	// CAN_BUSTIMING1 = 0x2F;		//sam = 0(sigle sample)
	 CAN_BUSTIMING0 = bustiming0;
	 CAN_BUSTIMING1 = bustiming1;
	 CAN_CLOCK_DIVIDER = 0x00;	//choose basic mode;
	 CAN_BASIC_ACCEP_CODE = accep_code;
	 CAN_BASIC_ACCEP_MASK = accep_mask;
}

//send a basic frame. used in non-irq functions.
void can_basic_send(char accep_code, char * data_ptr, char data_length)
{
 	EO = 0;
	CAN_TRANS_ID1 = accep_code;
	CAN_TRANS_ID2 = data_length;	//id2~id1 set to 0; rtr = 0; DLC is data_length <= 8

	CAN_TRANS_DATA1 = *data_ptr++;
	CAN_TRANS_DATA2 = *data_ptr++;
	CAN_TRANS_DATA3 = *data_ptr++;
	CAN_TRANS_DATA4 = *data_ptr++;
	CAN_TRANS_DATA5 = *data_ptr++;
	CAN_TRANS_DATA6 = *data_ptr++;
	CAN_TRANS_DATA7 = *data_ptr++;	
	CAN_TRANS_DATA8 = *data_ptr++;

	CAN_BASIC_COMMAND = 0x01;		//transfer request;

}

//send a basic frame. used in non-irq functions.
void can2_basic_send(char accep_code, char * data_ptr, char data_length)
{
 	EO = 0x80;
	CAN_TRANS_ID1 = accep_code;
	CAN_TRANS_ID2 = data_length;	//id2~id1 set to 0; rtr = 0; DLC is data_length <= 8

	CAN_TRANS_DATA1 = *data_ptr++;
	CAN_TRANS_DATA2 = *data_ptr++;
	CAN_TRANS_DATA3 = *data_ptr++;
	CAN_TRANS_DATA4 = *data_ptr++;
	CAN_TRANS_DATA5 = *data_ptr++;
	CAN_TRANS_DATA6 = *data_ptr++;
	CAN_TRANS_DATA7 = *data_ptr++;	
	CAN_TRANS_DATA8 = *data_ptr++;

	CAN_BASIC_COMMAND = 0x01;		//transfer request;
}

//read rx_buffer to ExRAM. used in no-irq functions.
void can_basic_receive()
{
	char temp_data[8];
	char i,temp;
	
	EO = 0x00;
	temp = CAN_RECEIVE_ID2;
	temp &= 0x0F;
	if(temp > 8) temp = 8;		//read the length of data
	temp_data[0] = CAN_RECEIVE_DATA1;
	temp_data[1] = CAN_RECEIVE_DATA2;
	temp_data[2] = CAN_RECEIVE_DATA3;		
	temp_data[3] = CAN_RECEIVE_DATA4;
	temp_data[4] = CAN_RECEIVE_DATA5;
	temp_data[5] = CAN_RECEIVE_DATA6;
	temp_data[6] = CAN_RECEIVE_DATA7;
	temp_data[7] = CAN_RECEIVE_DATA8;
	for(i=0;i<temp;i++)
	{
	 	*received_data++ = temp_data[i];
	}
}

//read rx_buffer to ExRAM. used in no-irq functions.
void can2_basic_receive()
{
	char temp_data[8];
	char i,temp;
	
	EO = 0x80;

	temp = CAN_RECEIVE_ID2;
	temp &= 0x0F;
	if(temp > 8) temp = 8;		//read the length of data
	temp_data[0] = CAN_RECEIVE_DATA1;
	temp_data[1] = CAN_RECEIVE_DATA2;
	temp_data[2] = CAN_RECEIVE_DATA3;		
	temp_data[3] = CAN_RECEIVE_DATA4;
	temp_data[4] = CAN_RECEIVE_DATA5;
	temp_data[5] = CAN_RECEIVE_DATA6;
	temp_data[6] = CAN_RECEIVE_DATA7;
	temp_data[7] = CAN_RECEIVE_DATA8;
	for(i=0;i<temp;i++)
	{
	 	*received_data++ = temp_data[i];
	}
}

//release rx buffer command. used in no-irq functions.
void can_basic_release_buffer()
{
	EO = 0x00;
	CAN_BASIC_COMMAND = 0x04;		//release rx buffer 0000_0100;
}

//release rx buffer command. used in no-irq functions.
void can2_basic_release_buffer()
{
	EO = 0x80;
	CAN_BASIC_COMMAND = 0x04;		//release rx buffer 0000_0100;
}

//polling trans/receive test   (test IR reg: when interrupt disable, read should be 0xE0)
void can_basic_polling_test()
{
	char ir_test = 0;
	char xdata * data_ptr;
	data_ptr = send_data;			//the address of data need to be sent
	received_data = 300;	//receive data storge at 0x300 in ex_ram
////////////////////////polling trans & receive test///////////////////////////////

//////////////////////////////can 1 send and can 2 receive ////////////////////////////////
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode

	 //frame 1 
	 can_basic_send(0xAB,data_ptr,1);	//send 1 byte
	 data_ptr += 1;
	 EO = 0x00;
	 
	 //frame 2
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,2);	//send 2 byte
	 data_ptr += 2;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 //frame 3
	 EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,3);	//send 3 byte
	 data_ptr += 3;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 //frame 4
	 EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,4);	//send 4 byte
	 data_ptr += 4;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();
 	 
	//frame 5
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,5);	//send 5 byte
	 data_ptr += 5;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 6
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,6);	//send 6 byte
	 data_ptr += 6;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 7
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,7);	//send 7 byte
	 data_ptr += 7;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 8
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,8);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 9
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,9);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 10
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,10);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 11
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,11);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 12
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,12);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 13
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,13);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 14
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,14);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 15
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,15);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;	//receive frame 14
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 EO = 0x80;	//receive frame 15
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp != 92)
	 {
		P0 = 'N' ;
		test_info("FAIL_can Basic_irq tran & rec test_1-2");
	 }
	  
//////////////////////////can 2 send and can 1 receive ///////////////////////////////////////

	 received_data = 300;	//receive data storge at 0x300 in ex_ram
	 data_ptr = send_data;			//the address of data need to be sent
	 //frame 1 
	 can2_basic_send(0xAB,data_ptr,1);	//send 1 byte
	 data_ptr += 1;
	 EO = 0x80;
	 
	 //frame 2
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_send(0xAB,data_ptr,2);	//send 2 byte
	 data_ptr += 2;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_release_buffer();

	 //frame 3
	 EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_send(0xAB,data_ptr,3);	//send 3 byte
	 data_ptr += 3;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_receive();
	 can_basic_release_buffer();

	 //frame 4
	 EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can2_basic_send(0xAB,data_ptr,4);	//send 4 byte
	 data_ptr += 4;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_receive();
	 can_basic_release_buffer();
 	 
	//frame 5
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,5);	//send 5 byte
	 data_ptr += 5;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 6
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,6);	//send 6 byte
	 data_ptr += 6;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 7
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,7);	//send 7 byte
	 data_ptr += 7;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 8
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,8);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 9
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,9);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 10
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,10);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 11
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,11);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 12
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,12);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 13
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,13);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 14
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,14);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 15
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can2_basic_send(0xAB,data_ptr,15);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;	//receive frame 14
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	 EO = 0x00;	//receive frame 15
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0xE0) ir_test = 1;	//when interrupt disable, IR should be 0x00 

	 can_basic_receive();
	 can_basic_release_buffer();

	//////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp == 92)
	 {
		P0 = 'Y' ;
		test_info("OK_can Basic_polling tran & rec test");
	 }
	 else
	 {
		P0 = 'N' ;
		test_info("FAIL_can Basic_irq tran & rec test_2-1");
	 }

	 ///interrupt reg should be 8'b11100000 when Interrupt disable
	 if( ir_test == 1)
	 {
	  	P0 = 'N';
		test_info("FAIL_can Basic_IR disable test");
	 }
	 else
	 {
	  	P0 = 'Y';
		test_info("OK_can Basic_IR disable test");
	 }
}

//trans & receive by irq test
void can_basic_irq_test()
{
////////////////interrupt trans & receive test/////////////////////
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x1E;//overflow enable, error enable, transfer enable, receive enable;
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x1E;//overflow enable, error enable, transfer enable, receive enable;
	 
	 accep_code_global = 0xAB; //set accep_code will be sent in irq
	 trans_data_ptr_irq = send_data; //data pointer used in irq
	 received_data = 300;		//set receive data address.
	 counter_global = 2;	   //data length.
	 counter_global_2 = 0;		//data have been receive.

	 can_basic_send(0xAB,trans_data_ptr_irq,1);
	 trans_data_ptr_irq ++;
	 
	 while(counter_global_2 != 15);	   //have receive 15 frames
	 
	 //////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp != 92)
	 {
		P0 = 'N' ;
		test_info("FAIL_can Basic_irq tran & rec test_1-2");
	 }

	 //////can2 SEND CAN 1 receive
	 trans_data_ptr_irq = send_data; //data pointer used in irq
	 received_data = 300;		//set receive data address.
	 counter_global = 2;	   //data length.
	 counter_global_2 = 0;		//data have been receive.

	 can2_basic_send(0xAB,trans_data_ptr_irq,1);
	 trans_data_ptr_irq ++;

	 while(counter_global_2 != 15);	   //have receive 15 frames

	 //////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp == 92)
	 {
		P0 = 'Y' ;
		test_info("OK_can Basic_irq tran & rec test");
	 }
	 else
	 {
		P0 = 'N' ;
		test_info("FAIL_can Basic_irq tran & rec test_2-1");
	 }
}

//send wrong ID test.
void can_basic_id_test()
{
	//////////////////send wrong ID test/////////////////////	
 	EO = 0;					//SET CAN 0;
	CAN_BASIC_CONTROL = 0x01;
	 CAN_BASIC_ACCEP_MASK = 0x00; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00;	//exit reset mode
	EO = 0x80;
	CAN_BASIC_CONTROL = 0x01;
	 CAN_BASIC_ACCEP_MASK = 0x00; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00; 	//exit reset mode
	
	
	/////CAN 1 SEND CAN 2 RECEIVE/////
	can_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x00;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;

	EO = 0x80; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //frame 2 should be received, frame 1 lost.
	
	// frame 1 lost ,frame 2 received, so there should be only 1 data in buffer and it's '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		test_info("FAIL_can basic_id test_wrong id test_1-2");
		P0 = 'N';
	}	  
	/////CAN 2 send CAN 1 RECEIVE /////
	can2_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x80;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can2_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;
	EO = 0x00; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //frame 2 should be received, frame 1 lost.
	// frame 1 lost ,frame 2 received, so there should be only 1 data in buffer and it's '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'N' ;
		test_info("FAIL_can basic_id test_wrong id test_2-1");
	}
	else
	{
		P0 = 'Y';
		test_info("OK_can basic_id test_wrong id test");
	}

	/////////////////accecptance mask disable test///////////////
	// change mask to 11111111 (all bits irrelevant)
 	EO = 0;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00;	//exit reset mode
	EO = 0x80;
	 CAN_BASIC_CONTROL = 0x01; //SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00; 	//exit reset mode

	 /////CAN 1 SEND CAN 2 RECEIVE/////
	can_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x00;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;

	EO = 0x80; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //both frame 1 & 2 should received.
	
	//buffer should exsit 2 bytes data : '1', '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '1'))
	{
		P0 = 'A' ;
		test_info("FAIL_can basic_id test_id mask test_1-2_p1");
	}
	can2_basic_release_buffer();

	EO = 0x80; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //frame 2 should received.

	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'B' ;
		test_info("FAIL_can basic_id test_id mask test_1-2_p2");
	}
	can2_basic_release_buffer();

	EO = 0x00;
	while( (~CAN_BASIC_STATUS) & 0x04);	//can 1 frame 2 send over

	/////CAN 2 send CAN 1 RECEIVE /////
	can2_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x80;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can2_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;
	EO = 0x00; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //both frame 1 & 2 received
	
	//buffer should exsit 2 bytes data : '1', '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '1'))
	{
		P0 = 'C' ;
		test_info("FAIL_can basic_id test_id mask test_2-1_p1");
	}
	can_basic_release_buffer();

	EO = 0x00; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //both frame 1 & 2 received

	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'D' ;
		test_info("FAIL_can basic_id test_id mask test_2-1_p2");
	}
	else	
	{
		P0 = 'Y' ;
		test_info("OK_can basic_id test_id mask test");
	}
	can_basic_release_buffer();

	//Initial mask setting
 	EO = 0;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00;	//exit reset mode
	EO = 0x80;
	 CAN_BASIC_CONTROL = 0x01; //SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00; 	//exit reset mode

} 




#endif


void can_basic_arbitration_test()
{
	EO = 0;
	CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	EO = 0x80;
	CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode

	EO = 0;
	CAN_TRANS_ID1 = 0xAB;
	CAN_TRANS_ID2 = 1;	
	CAN_TRANS_DATA1 = '1';
	CAN_BASIC_COMMAND = 0x01;		//transfer request;
	EO = 0x80;
	CAN_TRANS_ID1 = 0xAA;
	CAN_TRANS_ID2 = 1;	
	CAN_TRANS_DATA1 = '2';
	CAN_BASIC_COMMAND = 0x01;		//transfer request;
	
	EO= 0x00;
	while( (~CAN_BASIC_STATUS) & 0x01);	 //can 1 receive '2'
	if(CAN_RECEIVE_DATA1 != '2')
	{
		P0 = 'N';
		test_info("FAIL_can basic_arbitration test_P1");	 	
	}
	can_basic_release_buffer();

	EO = 0x80 ;

	if(CAN_BASIC_STATUS & 0x01)		//at this time, can 2 still not receiuve data '1'
  	{
		P0 = 'N';
		test_info("FAIL_can basic_arbitration test_P2");	 	
	}
	while((~CAN_BASIC_STATUS) & 0x01); //can 2 receive '1'
	if(CAN_RECEIVE_DATA1 != '1') 
	{
		P0 = 'N';
		test_info("FAIL_can basic_arbitration test_P3");	 	
	}
	else
	{
	 	P0 = 'Y';
		test_info("OK_can basic_arbitration test");
	}
	can2_basic_release_buffer();
}

void can_basic_remote_test()
{
 	char data_length;
	char temp1,temp2,temp3;

	EO = 0;
	CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	EO = 0x80;
	CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode

	//can 1 send remote frame to request 2 byte data from can2
	EO = 0;
	CAN_TRANS_ID1 = 0xAB;
	CAN_TRANS_ID2 = 0x12;	//id2~id1 set to 0; rtr = 1; DLC is data_length = 2

	CAN_TRANS_DATA1 = 'A';
	CAN_TRANS_DATA2 = 'B';
	CAN_TRANS_DATA3 = 'C';	//characters 'A,B,C' shouldn't be sent 

	CAN_BASIC_COMMAND = 0x01;		//transfer request;

	EO = 0x80;
	while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve remote frame
	temp1 = CAN_RECEIVE_DATA1;
	temp2 = CAN_RECEIVE_DATA2;
	temp3 = CAN_RECEIVE_DATA3;
	if(    temp1 == 'A' 
		|| temp2 == 'B' 
		|| temp3 == 'C' )	//CAN 2 receive inappropriate data
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P1");
	}
	
	if(!(CAN_RECEIVE_ID2 & 0x10))	//can 2 didn't found a RTR bit
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P2");
	}
	data_length = CAN_RECEIVE_ID2 & 0x0F;
	can2_basic_release_buffer();
	can2_basic_send(0xAB,send_data,data_length);	//can 2 return some data requested('1,2'

	EO = 0x00;
	while((~CAN_BASIC_STATUS) & 0x01);	//wait for can 1 receive the data can 2 returend
	if( CAN_RECEIVE_ID2 != 0x02)
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P3");
	}
	else if( CAN_RECEIVE_DATA1 != '1' || CAN_RECEIVE_DATA2 != '2')
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P4");
	}
	can_basic_release_buffer();											
	
	//can 2 send remote frame to request 2 byte data from can1
	EO = 0x80;
	CAN_TRANS_ID1 = 0xAB;
	CAN_TRANS_ID2 = 0x12;	//id2~id1 set to 0; rtr = 1; DLC is data_length = 2

	CAN_TRANS_DATA1 = 'A';
	CAN_TRANS_DATA2 = 'B';
	CAN_TRANS_DATA3 = 'C';	//characters 'A,B,C' shouldn't be sent 

	CAN_BASIC_COMMAND = 0x01;		//transfer request;

	EO = 0x00;
	while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve remote frame
	temp1 = CAN_RECEIVE_DATA1;
	temp2 = CAN_RECEIVE_DATA2;
	temp3 = CAN_RECEIVE_DATA3;
	if(    temp1 == 'A' 
		|| temp2 == 'B' 
		|| temp3 == 'C' )	//CAN 2 receive inappropriate data
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P5");
	}
	
	if(!(CAN_RECEIVE_ID2 & 0x10))	//can 2 didn't found a RTR bit
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P6");
	}
	data_length = CAN_RECEIVE_ID2 & 0x0F;
	can_basic_release_buffer();
	can_basic_send(0xAB,send_data,data_length);	//can 2 return some data requested('1,2'

	EO = 0x80;
	while((~CAN_BASIC_STATUS) & 0x01);	//wait for can 1 receive the data can 2 returend
	if( CAN_RECEIVE_ID2 != 0x02)
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P7");
	}
	else if( CAN_RECEIVE_DATA1 != '1' || CAN_RECEIVE_DATA2 != '2')
	{
	 	P0 = 'N';
		test_info("FAIL_can basic_remote test_P8");
	}	
	else
	{
	 	P0 = 'Y';
		test_info("OK_can basic_remote test");
	}

	

	

}





void can_basic_error_test()
{
 	 EO = 0;
	CAN_BASIC_CONTROL = 0x08;	//Only enalbe error interrupt
	EO = 0x80;
	CAN_BASIC_CONTROL = 0x08;	//Only enalbe error interrupt

	P0 = '@';					//tell TB " error test start!"
	can_basic_send(0xAB,send_data,1);

	while( (~CAN_BASIC_STATUS) & 0x04);	 //23th, txcnt=135, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //24th, txcnt=134, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //25th, txcnt=133, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //26th, txcnt=132, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //27th, txcnt=131, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //28th, txcnt=130, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //29th, txcnt=129, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //30th, txcnt=128, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);
	while( (~CAN_BASIC_STATUS) & 0x04);	 //31th, txcnt=127, success transfer 1 frame, cnt -1
 	can_basic_send(0xAB,send_data,1);

	while(P0!='Q');		//exit the reset mode
	EO = 0;
	CAN_BASIC_CONTROL = 0x08;	//error interrupt disable, exit reset mode	

	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty  for overload frame test
 	can_basic_send(0xAB,send_data,1);	 //this frame don't have inter frame, need one more
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty  for overload frame test
 	can_basic_send(0xAB,send_data,1);	//begin at inter frame, invert the 1,2 bit of inter.


	while(P0!='w');
	//wait tb's response
	


}




void can_basic_fifo_test()
{
	 char trans_cnt;
	 char recei_cnt;
	 char data_right;

//////////////////////////////can 2 send and can 1 receive ////////////////////////////////
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x10;	//all interrupt disable, exit reset mode
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x10;	//All interrupt disable, exit reset mode

	 received_data = 300;	//receive data storge at 0x300 in ex_ram
	 counter_global = 0;
	
	 EO = 0x80;
	 //send (2+8)x8 bytes	lead 2 overflow
	 for(trans_cnt = 1;trans_cnt <= 7;trans_cnt++)
	 {
	 	can2_basic_send(0xAB,send_data,8);	//send 1 byte
	 	while( (~CAN_BASIC_STATUS) & 0x04);
	 }
	 can2_basic_send(0xAB,send_data,8);	//send 1 byte	 	 

	 EO =80;	 
	 while( (~CAN_BASIC_STATUS) & 0x04);

	 for(trans_cnt = 1;trans_cnt <= 6; trans_cnt++)	//in fact receive 6 valid frame.
	 {
	 	can_basic_receive();
		can_basic_release_buffer();	
	 }

	//check recieve data, should be '12345678' x 6
	 	 recei_temp = 300;	//ptr point at the beginning of the receive data.
     data_right = 1;
	 for(trans_cnt = 1;trans_cnt <= 6;trans_cnt ++)
	 {
	 	trans_temp = 0x0000;
		for(recei_cnt=1;recei_cnt<=8;recei_cnt++)
		{
			if(*recei_temp != *trans_temp)	
			  data_right = 0;
		  	recei_temp ++;
			trans_temp ++;
		}
	 }
	 if(data_right == 1 && counter_global == 1)
	 {
	  	P0 = 'Y';
		test_info("OK_can Basic_overflow");
	 }
	 else
	 {
	  	P0 = 'N';
		test_info("FAIL_can Basic_overflow");
	 }

}

void can_receive_irq_and_stop_test()
{
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode
	 
	 EO = 0x80;
	 can2_basic_send(0xAB,send_data,1);	//send 1 byte
	 while( (~CAN_BASIC_STATUS) & 0x04);
	 can2_basic_send(0xAB,send_data,1);	//send 1 byte
	 while( (~CAN_BASIC_STATUS) & 0x04);
	 // stop transmit request test
	 can2_basic_send(0xAB,send_data,1);	//send 1 byte
	 while( ~CAN_BASIC_STATUS & 0x20 );
	 delay(15);
	 P0='D';
	 CAN_BASIC_COMMAND = 0x02;
	 //turn can 1 's receive interrupt enable
	 EO = 0x00;
	 CAN_BASIC_CONTROL = 0x02;
	 while(1);	 
	 
}



void can_bustiming_test()
{
	 
	 
	 //reset to normal
	 InitCan_Basic(0x43,0x2F,0xAB,0xFF); 
	 InitCan2_Basic(0x43,0x2F,0xAB,0xFF);
}